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You are building an integrated circuit where the clock driver shares 1-mm-long by 2-μm-wide power and ground wires with full-swing driver and receiver circuits. Suppose the clock driver and its 100-pF clock load are modeled as shown in Figure 6-28 by a switch, a 542 resistor, and 100-pF of capacitance to ground. Assume that the switch toggles every 2.5 ns to generate a 200-MHz square wave on the clock network. Sketch and dimension the local power and ground voltages, VLP and VLG, in Figure 6-28. How does this noise affect connection A in the figure? Connection B?

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