[an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction for example with multiple processor scenario or as part of an instruction being worked on by a processor. Because superscalar architectures provide a great liberty in the order in which instructions can be issued and completed]
Solved by delaying the execution of a certain instruction until it can be executed.
[They occur if two or more instructions compete for the same resource (register, memory, functional unit) at the same time; they are similar to structural hazards dis-cussed with pipelines.]
By introducing several parallel pipelined units, superscalar architectures try to reduce a part of possible re-source conflicts
[An instruction is control dependent on a preceding instruction if the outcome of latter determines whether former should be executed or not. If instructions are of variable length, they cannot be fetched and issued in parallel; fetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard – separate category because they are treated in different ways an instruction has to be decoded in order to identify the following one and to fetch it]