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This addressing mode is used only by the call instruction. A 30-bit displacement (taken from the
instruction) is padded to 32 bits by appending two zero bits and the result is added to the program counter (in fact, due to the way in which the fetch-execute cycle works, the value that is used is PC + 4). This results in no loss of functionality, since the SPARC instructions are all 32 bits wide, and therefore must be fetched from word aligned addresses in which the lower two bits will always be zero. This
addressing modes allows transfer of control to any instruction in the entire address space of the processor. The calculated address (known as the effective address) becomes the new value of the nPC register.

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