One of the simplifying factors about the SPARC’s RISC architecture is that all instructions are 32 bits wide. There are no exceptions to this rule. Compared with many CISC processors this greatly simplifies instruction fetching and decoding. The first two bits of an instruction (the opcode field) place it into one of three instruction classes. These classes are referred to as Format 1 instructions, Format 2 instructions and Format 3 instructions. Each of these formats has a different structure to be decoded.
The Format 1 instruction (there is only one) is the call instruction. Format 2 is used for the branch instructions and the sethi instruction, and Format 3 for the arithmetic and logical, and load and store.