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Tristate Logic Gates

Tristate logic gates have three possible output states, i.e. the logic ‘1’ state, the logic ‘0’ state and a high-impedance state. The high-impedance state is controlled by an external ENABLE input. The ENABLE input decides whether the gate is active or in the high-impedance state. When active, it can be ‘0’ or ‘1’ depending upon input conditions. One of the main advantages of these gates is that their inputs and outputs can be connected in parallel to a common bus line. shows the circuit symbol of a tristate NAND gate with active HIGH ENABLE input, along with its truth table. The one has active LOW ENABLE input. When tristate devices are paralleled, only one of them is enabled at a time. paralleling of tristate inverters having active HIGH ENABLE inputs.

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