The following guidelines should be adhered to while using CMOS family devices:
1. Proper handling of CMOS ICs before they are used and also after they have been mounted on the PC boards is very important as these ICs are highly prone to damage by electrostatic discharge. Although all CMOS ICs have inbuilt protection networks to guard them against electrostatic discharge, precautions should be taken to avoid such an eventuality. While handling unmounted chips, potential differences should be avoided. It is good practice to cover the chips with a conductive foil. Once the chips have been mounted on the PC board, it is good practice again to put conductive clips or conductive tape on the PC board terminals. Remember that PC board is nothing but an extension of the leads of the ICs mounted on it unless it is integrated with the overall system and proper voltages are present.
2. All unused inputs must always be connected to either VSS or VDD depending upon the logic involved. A floating input can result in a faulty logic operation. In the case of high-current device types such as buffers, it can also lead to the maximum power dissipation of the chip being exceeded, thus causing device damage. A resistor (typically 220 k to 1 M should preferably be connected between input and the VSS or VDD if there is a possibility of device terminals becoming temporarily unconnected or open.
3. The recommended operating supply voltage ranges are 3–12 V for A-series (3–15 V being the maximum rating) and 3–15 V for B-series and UB-series (3–18 V being the maximum). For CMOS IC application circuits that are operated in a linear mode over a portion of the voltage range, such as RC or crystal oscillators, a minimum VDD of 4 V is recommended.
4. Input signals should be maintained within the power supply voltage range VSS < Vi < VDD (−0.5 V < Vi < VDD + 0.5 V being the absolute maximum). If the input signal exceeds the recommended input signal range, the input current should be limited to ±100 mA.
5. CMOS ICs like active pull-up TTL ICs cannot be connected in WIRE-OR configuration. Paralleling of inputs and outputs of gates is also recommended for ICs in the same package only.
6. The majority of CMOS clocked devices have maximum rise and fall time ratings of normally 5–15 us.The device may not function properly with larger rise and fall times. The restriction, however, does not apply to those CMOS ICs that have inbuilt Schmitt trigger shaping in the clock circuit.