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1.         A system is based on an 8-bit microprocessor and has two I/O devices. The I/O controllers for this system use separate control and status registers. Both devices handle data on a 1-byte-​at-​a-​time basis. The first device has two status lines and three control lines. The second device has three status lines and four control lines.


a. How many 8-bit I/O control module registers do we need for status reading and control of

each device?




b. What is the total number of needed control module registers given that the first device is

an output-​only device?




c. How many distinct addresses are needed to control the two devices?






2.         A DMA module is transferring characters to memory using cycle stealing from a device

transmitting at 9600 bps. The processor is fetching instructions at the rate of 1 million

instructions per second (1 MIPS). By how much will the processor be slowed down due to the

DMA activity?






3.         Consider a system in which bus cycles takes 500 ns. Transfer of bus control in either

direction, from processor to I/O device or vice versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. Data are transferred 1 byte at a time.

a. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus

mastership prior to the start of a block transfer and maintains control of the bus until the

whole block is transferred. For how long would the device tie up the bus when

transferring a block of 128 bytes?


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